When fabricating semiconductor devices, for electrical connection between elements or lines, metal lines are used. In recent years, as semiconductor devices are required to have higher integration and higher performance, copper (Cu), having excellent electrical properties such as conductivity, is used as the material of choice to form the metal lines.
A copper metal line is not easy to pattern through an etching process, such as subtractive patterning process used to form aluminum metal lines, and so it is patterned through a damascene process. In a multi-line structure, a damascene process of forming a via connecting upper/lower lines and an upper metal line at the same time has widely been used.
FIG. 1 is a cross-sectional view of part of a simplified interconnect structure formed on a semiconductor device from the prior art. In the figure, a patterned dielectric layer 54 is formed on an upper surface of a semiconductor substrate 50. Formed between the openings of the patterned dielectric layer 54 are metal lines 55. A metal layer 56 made of copper, for instance is formed above the metal lines 55 and the patterned dielectric layer 54. In a later process, the metal layer will be etched to form metal vias above the lower metal lines 55. Though not shown in FIG. 1, a thin layer of bather metal film may be deposited and formed on the inner walls of the metal lines 55 and/or metal vias. The barrier metal film functions to prevent copper atoms from diffusing into the dielectric layer 54 when metal lines and/or metal vias are formed. Also shown in FIG. 1 is a patterned photoresist layer 58 formed on metal layer 56 through a typical photolithography process. The photolithography process may comprise a series of processes, such as photoresist coating, exposure, and development.
The conventional copper metal line formation method can have a number of problems however. One problem may be misalignment. In the process of device feature or pattern exposure, the alignment between successive layers that are being created is of critical importance. Smaller device dimensions place even more stringent requirements on the accuracy of the alignment of the successive layers that are superimposed on each other. In FIG. 2, following the etching of the metal layer 56 in which the patterned photoresist layer 58 is used as mask to form metal vias 60, via recesses VR may be formed at the juncture of a metal via 60 and a respective one of the lower metal line. Via recesses can be caused when the metal via 60 in contact with a respective one of the lower metal line are misaligned (e.g., shifted to one side) relative to the lower metal line. Such misalignment can result from a mask misalignment failure, for example, during the photolithography process. Due to this misalignment, the via recess formed can be a serious problem in the conventional copper etch approach by causing unstable yield and decreased device reliability.